8:1 multiplexer to 6:1 multiplexer











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I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.






multiplexer







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  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    3 hours ago








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    3 hours ago






  • 1




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    3 hours ago












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    53 mins ago















up vote
4
down vote

favorite












I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.






multiplexer







share|improve this question









New contributor




zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.




















  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    3 hours ago








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    3 hours ago






  • 1




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    3 hours ago












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    53 mins ago













up vote
4
down vote

favorite









up vote
4
down vote

favorite











I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.






multiplexer







share|improve this question









New contributor




zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.











I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.






multiplexer




multiplexer






share|improve this question









New contributor




zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.











share|improve this question









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zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.









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edited 1 hour ago









mike65535

9961619




9961619






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asked 3 hours ago









zaiz2s

211




211




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New contributor





zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.






zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.












  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    3 hours ago








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    3 hours ago






  • 1




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    3 hours ago












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    53 mins ago


















  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    3 hours ago








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    3 hours ago






  • 1




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    3 hours ago












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    53 mins ago
















Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
– Andy aka
3 hours ago






Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
– Andy aka
3 hours ago






1




1




You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
– analogsystemsrf
3 hours ago




You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
– analogsystemsrf
3 hours ago




1




1




Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
– Eugene Sh.
3 hours ago






Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
– Eugene Sh.
3 hours ago














Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
– Harry Svensson
53 mins ago




Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
– Harry Svensson
53 mins ago










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Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






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    Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






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      up vote
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      Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






      share|improve this answer























        up vote
        5
        down vote










        up vote
        5
        down vote









        Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






        share|improve this answer












        Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.







        share|improve this answer












        share|improve this answer



        share|improve this answer










        answered 3 hours ago









        Elliot Alderson

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