Suggestion regarding memory transfer in Opencl
0
I working on an Opencl Project on Xilinx FPGA's. The input data to the host code is not continuous, i.e; sporadic. If I transfer the data as it comes; the kernel will include memory transfer setup. This will significantly increase my kernel execution time. If I pack the data into an array and transfer the data the kernel will be stalled for N number of cycles/time. What is the best way to approach this problem.
kernel opencl
share | improve this question
asked Feb 4 at 3:39
user3751971 user3751971
1 1
...